This invention relates to memories, and more particularly to burst operations in memories.
To improve memory data rates, some memories support burst operations. In a burst operation, multiple memory locations are accessed in response to a single starting address. At the beginning of a burst operation, a row address AX (FIG. 1) is delivered to X-decoders 14. X-decoders 14 select the corresponding row of memory cells in memory array 12. (In FIG. 1, rows are vertical, and columns are horizontal.) The row remains selected for the duration of the burst operation. The starting column address AY is delivered to column address counter 18. Counter 18 counts up by 1 starting from address AY on each cycle of clock signal CLK, and provides the count A to Y-decoders 16. This causes Y-decoders 16 to select consecutive columns, at consecutive column addresses A, in consecutive cycles of clock CLK. As a result, the memory is accessed sequentially. The data D are transferred from the consecutive memory locations (i.e., memory locations at consecutive addresses) to an input/output (I/O) pad 30, or in the opposite direction, at the frequency of clock CLK. The data rate is improved because the same memory row remains selected for multiple memory locations and because, therefore, the row decoding need not be done for each memory location.
Disadvantageously, column address counter 18 operates at the same frequency as the data rate on I/O pad 30 (the frequency of clock CLK).
FIG. 2 shows a memory in which the column address counter 18 can operate at only half of the data rate on pad 30. The memory uses a two-bit prefetch technique known as "2n rule". The memory cells are arranged in two arrays 12.0, 12.1. Memory array 12.0 contains even memory locations (that is, memory locations at even column addresses; when a column address is even, the entire row-and-column address is even if the column address is the least significant portion of the entire address). Memory array 12.1 contains odd locations. In a burst operation, an even location in array 12.0 and an odd location in array 12.1 at consecutive addresses are accessed in parallel at one half of the frequency of clock CLK, and are transferred between the memory arrays and a buffer 36 at one half of the clock frequency. The data are transferred between buffer 36 and I/O pad 30 serially at the clock frequency.
The burst operation proceeds as follows. The row address (not shown) is supplied to both of the arrays 12.0, 12.1, to select one row in each array. Column address counter 18 receives the most significant bits AY[n:1] of the starting column address. The least significant bit AY[0] is not used by the counter. The counter counts up from AY[n:1] by 1 on every other clock cycle. The counter's output (count) signal A[n:1] is delivered to Y-decoder blocks 16.0, 16.1 of respective arrays 12.0, 12.1. Count bits A[n:1] are all but the least significant bit (LSB) of the column address.
Y-decoder blocks 16.0, 16.1 are identical. Y-decoder block 16.0 selects an even column. For this column, the column address LSB A[0]=0. Y-decoder block 16.1 select an odd column, corresponding to A[0]=1. As a result, two memory locations at column addresses &lt;A[n:1],0&gt;, &lt;A[n:1],1&gt; are accessed in parallel at one half of the clock frequency, with the data transferred to or from buffer 36. The data are transferred between buffer 36 and I/O pad 30 serially at the clock frequency.
The 2n rule memory of FIG. 2 is not well suited for burst operations that access memory non-sequentially or not at an even address boundary. Examples of such burst operations are burst operations defined by standards for synchronous dynamic random access memories (SDRAMs) and described in Table 1 below. The sequence of memory locations accessed in each burst operation of Table 1 is determined by the burst length (2, 4, or 8), burst mode (sequential or interleaved), and the three least significant bits AY[2:0] of the starting column address. The burst length and mode can be programmed into the SDRAM's mode register (not shown) before a READ or WRITE command is issued to the SDRAM for the burst operation.
TABLE 1 Starting Column Burst Address Data Sequence: Data Sequence: Length LSBs AY[2:0] Sequential Mode Interleave Mode 2 xx0 0,1 0,1 xx1 1,0 1,0 4 x00 0,1,2,3 0,1,2,3 x01 1,2,3,0 1,0,3,2 x10 2,3,0,1 2,3,0,1 x11 3,0,1,2 3,2,1,0 8 000 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7 001 1,2,3,4,5,6,7,0 1,0,3,2,5,4,7,6 010 2,3,4,5,6,7,0,1 2,3,0,1,6,7,4,5 011 3,4,5,6,7,0,1,2 3,2,1,0,7,6,5,4 100 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3 101 5,6,7,0,1,2,3,4 5,4,7,6,1,0,3,2 110 6,7,0,1,2,3,4,5 6,7,4,5,2,3,0,1 111 7,0,1,2,3,4,5,6 7,6,5,4,3,2,1,0
Columns 3 and 4 of Table 1 show the sequence in which the memory locations are accessed. For example, if the burst length is 4, the starting address is "x11" (i.e. AY[1:0]=11), and the mode is sequential, the locations are accessed in the order "3,0,1,2". This means the two LSBs A[1:0] of the accessed columns assume consecutively the values 3, 0, 1, 2 (binary 11, 00, 01, 10). The remaining column address bits A[n:2] are the same for each location, and are equal to the starting address bits AY[n:2]. For the burst length of 2, Table 1 provides the values of one LSB A[0] of the column address. The remaining column address bits A[n:1]=AY[n:1] are the same for each location accessed in the burst operation. For the burst length of 8, Table 1 provides the values of the three LSBs A[2:0]. The remaining address bits A[n:3]=AY[n:3] are the same for each location.
Each burst operation defined by Table 1 performs access to a block of consecutive memory locations, but the memory locations within the block can be accessed non-sequentially. The 2n-rule memory of FIG. 2 cannot prefetch data for non-consecutive locations. In addition, in Table 1, a burst operation can start at an odd address boundary. See for example the case of burst length=4, starting column address AY[2:0]=x01, sequential mode (locations 1,2 are to be accessed first, and they start at an odd address boundary). In the memory of FIG. 2, locations can be accessed in prefetch (i.e., in parallel) only if they start at an even address boundary. Therefore, there is a need for an alternative prefetch memory architecture that allows prefetches for non-consecutive memory locations and for locations starting at an odd column address boundary while allowing the address generation logic to operate at a lower rate than the data rate on the external input or output terminals (such as I/O pad 30).
Allowing the address generation logic to operate at a lower rate is particularly desirable in double data rate (DDR) SDRAMs which have emerged as a higher bandwidth memory solution than conventional SDRAMs. In DDR SDRAMs, data are provided on the external terminals on both the rising and falling clock edges. Thus, the data transfer rate is doubled. Address generation logic that can operate at a lower frequency is therefore particularly desirable.